1. Technical Field
The present disclosure relates to electrical devices, such as semiconductor devices. The present disclosure further relates to processing of materials suitable for the contacts to semiconductor devices.
2. Description of the Related Art
Semiconductor field effect transistors (FETs) continue to get smaller because of technological improvements in semiconductor fabrication processes. The technological improvements have enabled aggressive down-scaling of FETs, and the aggressive down-scaling has resulted in increased density of electrical components on integrated circuits. However, as FETs get smaller, challenges arise that can negatively impact their utility and performance. One challenge often encountered in semiconductor fabrication, which arises due to down-scaling of FETs, is the ability to provide FETs with low source/drain (S/D) contact resistance. A contact is an interface material between a FET substrate and interconnect wiring, wherein the interconnect wiring is routed to connect a FET to other integrated circuit components distributed on the surface of the substrate. A source/drain contact can enhance electrical current flow (i.e., reduce resistance) between substrate and interconnect wiring. However, as surface area of contacts decrease, due to the aggressive down-scaling, contact resistance can increase and cause a reduction of FET performance, such as a reduction in transistor switching speed.